1 Field of the invention
The present invention relates to a semiconductor memory device, and more specifically, to a semiconductor memory device having a split data transfer function.
2 Description of related art
In the prior art, this type of semiconductor memory has been used as an image display memory for a CRT (cathode ray tube) display and other displays. When a split data transfer is performed, a refresh operation is executed for all memory cells on one word line selected by a given row address, so that data stored in each of the memory cells on the selected word line is amplified and then rewritten to the same memory cell, and a portion of the amplified data is transferred to a data register.
Referring to U.S. Pat. No. 4,855,959 to Kobayashi, there is shown one typical conventional example of the semiconductor memory device having a split data transfer function. In this semiconductor memory device, a memory cell matrix of the semiconductor memory device is halved in function of the split data transfer operation in such a manner that each of word lines is halved into a lower portion and an upper portion, so that digit lines are also halved into a lower group of digit lines and an upper group of digit lines, and in addition, a date register is correspondingly halved into an upper portion and an upper portion.
When a split data transfer is performed, word lines of the semiconductor memory device are sequentially selected as follows:
In a first operation of split data transfer, data stored in the lower portion of a (0)th word line is transferred through the lower group of digit lines to the lower portion of the data register. Thereafter, the data stored in the lower portion of the data register is sequentially read out to the outside of the memory device in synchronism with clock signals supplied to the memory device. In the way of the data reading-out from the lower portion of the data register, a second operation of split data transfer is performed, so that data stored in the upper portion of the (0)th word line is transferred through the upper group of digit lines to the upper portion of the data register. The above mentioned operation is repeated for each of the remaining words lines in the order, so that the data stored in the memory device is serially and continuously outputted.
Here, attention is focused on the refresh operation carried out concurrently with the split data transfer. In the first operation of split data transfer performed for the lower portion of the (0)th word line, the refresh operation is carried out not only for all the memory cells included in the lower portion of the (0)th word line but also for the memory cells included in the upper portion of the (0)th word line. In addition, in the second operation of split data transfer performed for the upper portion of the (0)th word line, the refresh operation is also carried out not only for all the memory cells of the upper portion of the (0)th word line, but also for the memory cells of the lower portion of the (0)th word line. Namely, the refresh operation is executed for the same memory cells two times within a very short period of time. However, it is sufficient if the refresh operation is performed only one time within a predetermined or standardized period of time for each of the memory cells. In other words, one of the refresh operations executed two times within the very short period of time for all the memory cells of the same word line is not necessary, and rather, wasteful from a viewpoint of efficiency in the refresh operation.
The conventional semiconductor memory device having the split data transfer function has been proposed as the image display memory for the CRT display and other displays, which have a nature or restriction in which image information is required to be periodically and sequentially supplied by units of one pixel. The conventional semiconductor memory device has been satisfactory from the viewpoint of function in the image display memory. As mentioned above, however, the conventional semiconductor memory device has been disadvantageous in that the refresh operation is less efficient.